3-minute fever 三分鐘熱度

Have been kept this post in draft for quite some times. Not sure when I'll start with my next topic. So, I decided to post this first. Here's the first chapter, object oriented concept. Let’s go through an example before explore the object oriented jargons. Say, there is a book shelf. We have some books, a pen holder, pens, pencils, sharpener in the book shelf as illustrated below. These objects are related to each other in some ways. The bookshelf contains books, pens, pencils, pen holder and sharpener. The sharpener is used to sharpen the pencil. The pen holder holds the pens and pencils. There is variety of books in the bookshelf. How is this related to object oriented concept? Class A class is a collection of objects that has something in common. Say, we have a class of book. All books are classified in the class of book. Object Object is something real that exists. It is classified with other objects that share some common attributes into class. We can ...

To get code coverage percentage : /usr/perl -MDevel::Cover <perl scripts> <arguments> The code coverage database will be stored at a directory called : cover_db/ It will report out how many percentage hit per run. If you would like to view the total percentage hit result, you'll need to use another command : /usr/bin/cover This will report out the overall hit result. However, somehow I can’t' find which line of my perl scripts has not been hit to put more test for my test suite. Example output : ----------------------------------- ------ ------ ------ ------ ------ ------ File stmt branch cond sub time total ----------------------------------- ------ ------ ------ ------ ------ ------ hello2.pl 90.9 50.0 n/a 100.0 100.0 85.7 Total 90.9 50.0 n/a 100.0 100.0 85.7 ----------------------------------- ------ ------ ------ ------ ------ ------ Another way of doing this, but this doesn't report the hit in percentage, but list out how many hits on e...

Open a file, then type the following commands : :syntax on :set syntax=verilog The syntax files are the .vim files, you can use locate to look for it. Example : locate verilog.vim In the directory, you'll see the list of syntax that your vi is supporting. To make the syntax turn on by default to the language that you preferred, you can edit this file : vi ~/.vimrc Put these lines into the .vimrc file. syntax on set syntax=verilog Thanks to YZ shared this tips with me December last year. :)

I was lazy to do conversion from a source to MySQL database record, thus it is in original format, stored as string. E.g : Aug 23 2010 07:00PM Later, after a long while, I was requested to sort the query output from MySQL database, sort by the date! It is too late to do conversion, and repopulate the table, so... I found this : str_to_date. str_to_date(`date_str`, '%b %d %Y %h:%i%p') Example usage : SELECT str_to_date ('Aug 23 2010 07:00PM', '%b %d %Y %h:%i%p') as date It will return you this : 2010-08-23 19:00:00 Then you can sort the date accordingly. :) ORDER BY str_to_date(`date_str`, '%b %d %Y %h:%i%p') For the specifier, you can refer to http://dev.mysql.com/doc/refman/5.0/en/date-and-time-functions.html#function_date-format

Problem statement : Checking 2 paths if they are from the same path. In UNIX, we sometimes have softlinks to path. This has caused the path checking using pattern mathching is insufficient. After much workarounds in my codes, finally, I found this. I just get the absolute path from the 2 given paths, then make comparison. use Cwd 'abs_path'; if (abs_path($path1) eq abs_path($path2)) { ... ... } :)

To extract values from a variable. Say, $var = “10WW51”; ($yy,$ww) = ($var =~ /(\d\d)WW(\d\d)/); You’ll have $yy = 10, and $ww = 51. For this example, you can use split function, but for more complicated pattern, say, $var = “This WW data is from 10WW51.”; You’ll have a more complex way to extract the year and week information if you are using split function.

The easiest way, use DVE right-click on the signal, and do “Force Value”, then “Set Force…”, and do the necessary value setup. Some might run the test in ucli, or have the regression to be run automated by using tcl/do file, then you’ll need to know more about the force command construction. You can do a force –help in ucli or DVE command line for the help guide. Simple force value to signal command To set a signal to value 1 force <hierarchy.signal> 1 To set a signal to value 1 at time 10ns force <hierarchy.signal> 1 @10ns To set a signal to value 1 after 10ns from current time force <hierarchy.signal> 1 10ns The above commands are similar to force –freeze, which other activity in the simulation cannot override the value. To counter this, use –deposit in the force command. Force clocking value to a signal To set a clock signal with period 20ns, 60% duty cycle. What the following command will do is, force this signal to 1 at 0ns, then 0 at 12ns...

To dump a giant data structure and value in Perl. use Data::Dumper; $Data::Dumper::Indent = 3; print Dumper(%args);

This is my first post. I put on hold to start write anything as I am still not sure how shall I organize this, or what to put in this blog. Anyway, I should have starting point, and just go ahead from it. Let me start with the question asked by a DE today. Question : What is the difference between task and function in SystemVerilog? Task can have time control statements and delay, while function doesn’t support time control statement. Function can have return value, but task cannot. Task can call other task/functions, but function cannot call a task. (This limitation is on Verilog, SystemVerilog allow function to call a task using spawned thread.) A function must have at least one input argument, while task can have no arguments at all. Some notes. Both task and function support input, output, inout as their argument. For inout type, the argument act as input at the beginning and as output at the end of the routine. If a task that does not consume time, it is advisable to make it a voi...