The easiest way, use DVE right-click on the signal, and do “Force Value”, then “Set Force…”, and do the necessary value setup.
Some might run the test in ucli, or have the regression to be run automated by using tcl/do file, then you’ll need to know more about the force command construction.
You can do a force –help in ucli or DVE command line for the help guide.
Simple force value to signal command
To set a signal to value 1
force <hierarchy.signal> 1
To set a signal to value 1 at time 10ns
force <hierarchy.signal> 1 @10ns
To set a signal to value 1 after 10ns from current time
force <hierarchy.signal> 1 10ns
The above commands are similar to force –freeze, which other activity in the simulation cannot override the value. To counter this, use –deposit in the force command.
Force clocking value to a signal
To set a clock signal with period 20ns, 60% duty cycle. What the following command will do is, force this signal to 1 at 0ns, then 0 at 12ns, repeat the similar forces after 20ns.
force <hierarchy.signal> 1 0ns, 0 12ns –repeat 20ns
There is one more switch in this command call –cancel. It takes in the time as its input, to cancel the force command after the specified time.
For VHDL signal, need to add –drive switch to the force commands.