Values “extraction” in Perl

To extract values from a variable.

Say,

$var = “10WW51”;
($yy,$ww) = ($var =~ /(\d\d)WW(\d\d)/);

You’ll have $yy = 10, and $ww = 51.

For this example, you can use split function, but for more complicated pattern, say,

$var = “This WW data is from 10WW51.”;

You’ll have a more complex way to extract the year and week information if you are using split function.

force commands in VCSMX

The easiest way, use DVE right-click on the signal, and do “Force Value”, then “Set Force…”, and do the necessary value setup.

Some might run the test in ucli, or have the regression to be run automated by using tcl/do file, then you’ll need to know more about the force command construction.

You can do a force –help in ucli or DVE command line for the help guide.

Simple force value to signal command

To set a signal to value 1

force <hierarchy.signal> 1

To set a signal to value 1 at time 10ns

force <hierarchy.signal> 1 @10ns

To set a signal to value 1 after 10ns from current time

force <hierarchy.signal> 1 10ns

The above commands are similar to force –freeze, which other activity in the simulation cannot override the value. To counter this, use –deposit in the force command.

Force clocking value to a signal

To set a clock signal with period 20ns, 60% duty cycle. What the following command will do is, force this signal to 1 at 0ns, then 0 at 12ns, repeat the similar forces after 20ns.

force <hierarchy.signal> 1 0ns, 0 12ns –repeat 20ns

There is one more switch in this command call –cancel. It takes in the time as its input, to cancel the force command after the specified time.

For VHDL signal, need to add –drive switch to the force commands.

Dumper in Perl

To dump a giant data structure and value in Perl.

use Data::Dumper;
$Data::Dumper::Indent = 3;
print Dumper(%args);

Task and Function in SystemVerilog

This is my first post. I put on hold to start write anything as I am still not sure how shall I organize this, or what to put in this blog. Anyway, I should have starting point, and just go ahead from it. Let me start with the question asked by a DE today.

Question : What is the difference between task and function in SystemVerilog?

1. Task can have time control statements and delay, while function doesn’t support time control statement.
2. Function can have return value, but task cannot.
3. Task can call other task/functions, but function cannot call a task. (This limitation is on Verilog, SystemVerilog allow function to call a task using spawned thread.)
4. A function must have at least one input argument, while task can have no arguments at all.

Some notes.

1. Both task and function support input, output, inout as their argument.
2. For inout type, the argument act as input at the beginning and as output at the end of the routine.
3. If a task that does not consume time, it is advisable to make it a void function, so it can be called from any task or function.